1. Field
This disclosure relates generally to integrated circuits, and more specifically, to a hybrid transistor based power gating switch circuit and method.
2. Related Art
Switch circuits constitute a considerable portion of today's low power integrated circuits in order to reduce chip leakage power. More and more logic circuitry, memories and integrated circuit cores are now gated by different types of switch circuits, wherein the switch circuits could make up to five percent (5%) of total chip area. For 65 nm technology, a common switch transistor includes a logic low power (LP) PMOS transistor (also referred to as a “header” transistor) or a logic LP NMOS transistor (also referred to as a “footer” transistor); however, in 45 nm technology, due to oxide thickness reduction and increased gate leakage, as well as gate induced drain leakage (GIDL), the use of the core logic transistor as a switch has become more difficult. In particular, the gate and GIDL leakage of the core logic transistor exceeds the acceptable leakage budget for switch usage.
An alternative to the core logic transistor as a switch is an input/output (IO) transistor due to its thicker oxide which can allow for significantly less gate and GIDL leakage. However, while the leakage of the IO transistor as a switch is not a problem, the use of the IO transistor as a switch disadvantageously results in an undesirably significant area increase due to thick gate oxide design rules of the IO transistor, as well as lower transistor performance as compared to the core logic transistor.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.